1. Field of the Invention
The present invention relates to an arithmetic circuit, an arithmetic method, and an information processing device, which can correct an error that occurs at the time of a floating point arithmetic.
2. Description of the Related Art
For finer-line processes with the advance of a semiconductor manufacturing process, by way of example, also reductions in a wire width used for a semiconductor are in progress. As a result, the higher-level integration of a semiconductor proceeds, but at the same time, the probability of misoperation of a circuit increases.
Especially, in a supercomputer that performs a large-scale scientific technical calculation, many floating point arithmetic units are used, and a risk such that a misoperation occurs in one of the floating point arithmetic units due to the collision of radiation particles, which is caused by an alpha ray or a cosmic ray, and a calculation result becomes incorrect increases.
For example, if the failure rate of one floating point arithmetic unit is assumed to be 10 FIT (Failure In Time: rate at which one failure occurs per one hundred million hours), an error occurs in any of the floating point arithmetic units with a frequency of once per one hundred hours in a super computer that uses one million floating point arithmetic units.
As a method for detecting an error of a floating point arithmetic unit, a method for causing two identical arithmetic units to run in parallel, and for making a comparison between results of both of the arithmetic units exists. However, since this method requires arithmetic units and comparison circuits the numbers of which are twice as many as usual, a circuit amount significantly increases, and a burden on a supercomputer, which requires many floating point arithmetic units, becomes heavy.
Additionally, also an error of a principal portion of a floating point arithmetic unit can be detected also with a method such as parity prediction in an adder, and Modulo 3 residue check in a multiplier, and the like. However, with the parity check, an error cannot be detected when the number of error bit is even. Furthermore, with the Modulo 3 residue check, an error of the same residue cannot be detected. Still further, a circuit amount of 20 percent or more of an arithmetic unit itself must be added to detect an error in order to make these checks.
Japanese Published Patent Application No. H6-083591 discloses a floating point arithmetic unit that facilitates the detection of a failure of a gate positioned in a low order of a binary multiplier by selectively making and observing the output of a round off/digit aligner, and the output of low-order m bits.
As described above, an arithmetic circuit and a computer system, which detect an error that is problematic in a floating point arithmetic, with high probability and with a circuit amount as least as possible is desired, and besides, an arithmetic circuit and a computer system, which can correct an intermittent error caused by the collision of radiation particles, etc. by reexecuting an arithmetic instruction upon detection of an error, are desired.